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? 2003 microchip technology inc. ds21204d-page 1 25aa040/25lc040/25c040 device selection table features ? low-power cmos technology - write current: 3 ma typical - read current: 500 a typical - standby current: 500 na typical 512 x 8-bit organization 16 byte page write cycle time: 5 ms max. self-timed erase and write cycles block write protection - protect none, 1/4, 1/2 or all of array built-in write protection - power on/off data protection circuitry - write enable latch - write-protect pin sequential read high reliability - endurance: 1m cycles - data retention: > 200 years - esd protection: > 4000v 8-pin pdip, soic, and tssop packages temperature ranges supported: description the microchip technology inc. 25aa040/25lc040/ 25c040 (25xx040 * ) is a 4 kbit serial electrically erasable prom. the memory is accessed via a simple serial peripheral interface? (spi?) compatible serial bus. the bus signals required are a clock input (sck) plus separate data in (si) and data out (so) lines. access to the device is controlled through a chip select (cs ) input. communication to the device can be paused via the hold pin (hold ). while the device is paused, transi- tions on its inputs will be ignored, with the exception of chip select, allowing the host to service higher priority interrupts. also, write operations to the device can be disabled via the write-protect pin (wp ). package types block diagram part number v cc range max. clock frequency temp. ranges 25aa040 1.8-5.5v 1 mhz i 25lc040 2.5-5.5v 2 mhz i 25c040 4.5-5.5v 3 mhz i,e - industrial (i): -40 cto +85 c - automotive (e) (25c040): -40c to +125c cs so wp v ss v cc hold sck si 1 2 3 4 8 7 6 5 25xx040 cs so wp v ss v cc hold sck si 1 2 3 4 8 7 6 5 25xx040 hold v cc cs so 1 2 3 4 8 7 6 5 sck si v ss wp 25xx040 pdip soic tssop si so sck cs hold wp status register i/o control memory control logic hv generator eeprom array page y decoder sense amp. r/w control logic v cc v ss xdec latches 4k spi ? bus serial eeprom *25xx040 is used in this doc ument as a generic part number for the 25aa040/25lc040/25c040 devices. spi is a trademark of motorola corporation.
25aa040/25lc040/25c040 ds21204d-page 2 ? 2003 microchip technology inc. 1.0 electrical characteristics absolute maximum ratings (?) v cc ............................................................................................................................... ..............................................7.0v all inputs and outputs w.r.t. v ss .......................................................................................................... -0.6v to v cc +1.0v storage temperature ............................................................................................................ .....................-65c to 150c ambient temperature under bias ................................................................................................. ..............-65c to 125c esd protection on all pins ..................................................................................................... .................................... 4 kv table 1-1: dc characteristics ? notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for an extended period of time may affect device reliability dc characteristics industrial (i): t a = -40c to +85c v cc = 1.8v to 5.5v automotive (e): t a = -40c to +125c v cc = 4.5v to 5.5v (25c040 only) param. no. sym. characteristic min. max. units test conditions d001 v ih 1 high-level input voltage 2.0 v cc +1 v v cc 2.7v (note) d002 v ih 2 0.7 v cc v cc +1 v v cc < 2.7v (note) d003 v il 1 low-level input voltage -0.3 0.8 v v cc 2.7v (note) d004 v il 2 -0.3 0.3 v cc vv cc < 2.7v (note) d005 v ol low-level output voltage ?0.4vi ol = 2.1 ma d006 v ol ?0.2vi ol = 1.0 ma, v cc < 2.5v d007 v oh high-level output voltage v cc -0.5 ? v i oh =-400 a d008 i li input leakage current ? 1 acs = v cc , v in = v ss to v cc d009 i lo output leakage current ?1 acs = v cc , v out = v ss to v cc d010 c int internal capacitance (all inputs and outputs) ?7pft a = 25c, clk = 1.0 mhz, v cc = 5.0v (note) d011 i cc read operating current ? ? 1 500 ma a v cc = 5.5v; f clk = 3.0 mhz; so = open v cc = 2.5v; f clk = 2.0 mhz; so = open d012 i cc write ? ? 5 3 ma ma v cc = 5.5v v cc = 2.5v d013 i ccs standby current ? ? 5 1 a a cs = v cc = 5.5v, inputs tied to v cc or v ss cs = v cc = 2.5v, inputs tied to v cc or v ss note: this parameter is periodically sampled and not 100% tested.
? 2003 microchip technology inc. ds21204d-page 3 25aa040/25lc040/25c040 table 1-2: ac characteristics ac characteristics industrial (i): t a = -40c to +85c v cc = 1.8v to 5.5v automotive (e): t a = -40c to +125c v cc = 4.5v to 5.5v (25c040 only) param no. sym. characteristic min. max. units test conditions 1f clk clock frequency ? ? ? 3 2 1 mhz mhz mhz v cc = 4.5v to 5.5v v cc = 2.5v to 4.5v v cc = 1.8v to 2.5v 2t css cs setup time 100 250 500 ? ? ? ns ns ns v cc = 4.5v to 5.5v v cc = 2.5v to 4.5v v cc = 1.8v to 2.5v 3t csh cs hold time 150 250 475 ? ? ? ns ns ns v cc = 4.5v to 5.5v v cc = 2.5v to 4.5v v cc = 1.8v to 2.5v 4t csd cs disable time 500 ? ns ? 5t su data setup time 30 50 50 ? ? ? ns ns ns v cc = 4.5v to 5.5v v cc = 2.5v to 4.5v v cc = 1.8v to 2.5v 6t hd data hold time 50 100 100 ? ? ? ns ns ns v cc = 4.5v to 5.5v v cc = 2.5v to 4.5v v cc = 1.8v to 2.5v 7t r clk rise time ? 2 s (note 1) 8t f clk fall time ? 2 s (note 1) 9t hi clock high time 150 230 475 ? ? ? ns ns ns v cc = 4.5v to 5.5v v cc = 2.5v to 4.5v v cc = 1.8v to 2.5v 10 t lo clock low time 150 230 475 ? ? ? ns ns ns v cc = 4.5v to 5.5v v cc = 2.5v to 4.5v v cc = 1.8v to 2.5v 11 t cld clock delay time 50 ? ns ? 12 t cle clock enable time 50 ? ns ? 13 t v output valid from clock low ? ? ? 150 230 475 ns ns ns v cc = 4.5v to 5.5v v cc = 2.5v to 4.5v v cc = 1.8v to 2.5v 14 t ho output hold time 0 ? ns (note 1) 15 t dis output disable time ? ? ? 200 250 500 ns ns ns v cc = 4.5v to 5.5v (note 1) v cc = 2.5v to 4.5v (note 1) v cc = 1.8v to 2.5v (note 1) 16 t hs hold setup time 100 100 200 ? ? ? ns ns ns v cc = 4.5v to 5.5v v cc = 2.5v to 4.5v v cc = 1.8v to 2.5v 17 t hh hold hold time 100 100 200 ? ? ? ns ns ns v cc = 4.5v to 5.5v v cc = 2.5v to 4.5v v cc = 1.8v to 2.5v 18 t hz hold low to output high-z 100 150 200 ? ? ? ns ns ns v cc = 4.5v to 5.5v (note 1) v cc = 2.5v to 4.5v (note 1) v cc = 1.8v to 2.5v (note 1) 19 t hv hold high to output valid 100 150 200 ? ? ? ns ns ns v cc = 4.5v to 5.5v v cc = 2.5v to 4.5v v cc = 1.8v to 2.5v 20 t wc internal write cycle time ? 5 ms ? 21 ? endurance 1m ? e/w cycles (note 2) note 1: this parameter is periodically sampled and not 100% tested. 2: this parameter is not tested but ensured by characterizati on. for endurance estimates in a specific application, please consult the total endurance? m odel which can be obtained from our web site: www.microchip.com.
25aa040/25lc040/25c040 ds21204d-page 4 ? 2003 microchip technology inc. figure 1-1: hold timing figure 1-2: serial input timing figure 1-3: serial output timing cs sck so si hold 17 16 16 17 19 18 don?t care 5 high-impedance n+2 n+1 n n-1 n n+2 n+1 n n n-1 cs sck si so 6 5 8 7 11 3 lsb in msb in high-impedance 12 mode 1,1 mode 0,0 2 4 cs sck so 10 9 13 msb out isb out 3 15 don?t care si mode 1,1 mode 0,0 14
? 2003 microchip technology inc. ds21204d-page 5 25aa040/25lc040/25c040 table 1-3: ac test conditions figure 1-4: ac test circuit ac ac waveform: v lo = 0.2v ? v hi = v cc - 0.2v (note 1) v hi = 4.0v (note 2) timing measurement reference level input 0.5 v cc output 0.5 v cc note 1: for v cc 4.0v 2: for v cc > 4.0v v cc so 100 pf 1.8 k ? 2.25 k ?
25aa040/25lc040/25c040 ds21204d-page 6 ? 2003 microchip technology inc. 2.0 pin descriptions the descriptions of the pins are listed in table 2-1. table 2-1: pin function table 2.1 chip select (cs ) a low level on this pin selects the device. a high level deselects the device and forces it into standby mode. however, a programming cycle which is already initiated or in progress will be completed, regardless of the cs input signal. if cs is brought high during a program cycle, the device will go in standby mode as soon as the programming cycle is complete. when the device is deselected, so goes into the high-impedance state, allowing multiple parts to share the same spi bus. a low-to-high transition on cs after a valid write sequence initiates an internal write cycle. after power- up, a low level on cs is required prior to any sequence being initiated. 2.2 serial output (so) the so pin is used to transfer data out of the 25xx040. during a read cycle, data is shifted out on this pin after the falling edge of the serial clock. 2.3 write-protect (wp ) this pin is a hardware write-protect input pin. when wp is low, all writes to the array or status register are disabled, but any other operation functions normally. when wp is high, all functions, including nonvolatile writes operate normally. wp going low at any time will reset the write enable latch and inhibit programming, except when an internal write has already begun. if an internal write cycle has already begun, wp going low will have no effect on the write. see table 3-2 for write- protect functionality matrix. 2.4 serial input (si) the si pin is used to transfer data into the device. it receives instructions, addresses and data. data is latched on the rising edge of the serial clock. 2.5 serial clock (sck) the sck is used to synchronize the communication between a master and the 25xx040. instructions, addresses or data present on the si pin are latched on the rising edge of the clock input, while data on the so pin is updated after the falling edge of the clock input. 2.6 hold (hold ) the hold pin is used to suspend transmission to the 25xx040 while in the middle of a serial sequence with- out having to retransmit the entire sequence again at a later time. it must be held high any time this function is not being used. once the device is selected and a serial sequence is underway, the hold pin may be pulled low to pause further serial communication with- out resetting the serial sequence. the hold pin must be brought low while sck is low, otherwise the hold function will not be invoked until the next sck high-to- low transition. the 25xx040 must remain selected dur- ing this sequence. the si, sck and so pins are in a high-impedance state during the time the part is paused and transitions on these pins will be ignored. to resume serial communication, hold must be brought high while the sck pin is low, otherwise serial communication will not resume. lowering the hold line at any time will tri-state the so line. name pdip soic tssop description cs 1 1 3 chip select input so 2 2 4 serial data output wp 3 3 5 write-protect pin v ss 4 4 6 ground si 5 5 7 serial data input sck 6 6 8 serial clock input hold 7 7 1 hold input v cc 8 8 2 supply voltage
? 2003 microchip technology inc. ds21204d-page 7 25aa040/25lc040/25c040 3.0 functional description 3.1 principles of operation the 25xx040 is a 512 byte serial eeprom designed to interface directly with the serial peripheral interface (spi) port of many of today?s popular microcontroller families, including microchip?s pic16c6x/7x micro- controllers. it may also interface with microcontrollers that do not have a built-in spi port by using discrete i/o lines programmed properly with the software. the 25xx040 contains an 8-bit instruction register. the part is accessed via the si pin, with data being clocked in on the rising edge of sck. the cs pin must be low and the hold pin must be high for the entire operation. the wp pin must be held high to allow writing to the memory array. table 3-1 contains a list of the possible instruction bytes and format for device operation. the most significant address bit (a8) is located in the instruction byte. all instructions, addresses, and data are transferred msb first, lsb last. data is sampled on the first rising edge of sck after cs goes low. if the clock line is shared with other periph- eral devices on the spi bus, the user can assert the hold input and place the 25xx040 in ?hold? mode. after releasing the hold pin, operation will resume from the point when the hold was asserted. 3.2 read sequence the part is selected by pulling cs low. the 8-bit read instruction with the a8 address bit is transmitted to the 25xx040 followed by the lower 8-bit address (a7 through a0). after the correct read instruction and address are sent, the data stored in the memory at the selected address is shifted out on the so pin. the data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses. the internal address pointer is automatically incremented to the next higher address after each byte of data is shifted out. when the highest address is reached (01ffh), the address counter rolls over to address 0000h allowing the read cycle to be continued indefinitely. the read operation is terminated by raising the cs pin (figure 3-1). 3.3 write sequence prior to any attempt to write data to the 25xx040, the write enable latch must be set by issuing the wren instruction (figure 3-4). this is done by setting cs low and then clocking out the proper instruction into the 25xx040. after all eight bits of the instruction are transmitted, the cs must be brought high to set the write enable latch. if the write operation is initiated immediately after the wren instruction without cs being brought high, the data will not be written to the array because the write enable latch will not have been properly set. once the write enable latch is set, the user may proceed by setting the cs low, issuing a write instruction, followed by the address, and then the data to be written. keep in mind that the most significant address bit (a8) is included in the instruction byte. up to 16 bytes of data can be sent to the 25xx040 before a write cycle is necessary. the only restriction is that all of the bytes must reside in the same page. a page address begins with xxxx 0000 and ends with xxxx 1111 . if the internal address counter reaches xxxx 1111 and the clock continues, the counter will roll back to the first address of the page and overwrite any data in the page that may have been written. for the data to be actually written to the array, the cs must be brought high after the least significant bit (d0) of the n th data byte has been clocked in. if cs is brought high at any other time, the write operation will not be completed. refer to figure 3-2 and figure 3-3 for more detailed illustrations on the byte write sequence and the page write sequence respectively. while the write is in progress, the status register may be read to check the status of the wip, wel, bp1 and bp0 bits (figure 3-6). a read attempt of a memory array location will not be possible during a write cycle. when the write cycle is completed, the write enable latch is reset. table 3-1: instruction set instruction name instruction format description read 0000 a 8 011 read data from memory array beginning at selected address write 0000 a 8 010 write data to memory array beginning at selected address wrdi 0000 0100 reset the write enable latch (disable write operations) wren 0000 0110 set the write enable latch (enable write operations) rdsr 0000 0101 read status register wrsr 0000 0001 write status register note: a 8 is the 9 th address bit necessary to fully address 512 bytes.
25aa040/25lc040/25c040 ds21204d-page 8 ? 2003 microchip technology inc. figure 3-1: read sequence figure 3-2: byte write sequence figure 3-3: page write sequence so si sck cs 0 23456789101112131415161718192021 22 1 01 a8 0 0 0 01a7654 1a0 76543210 instruction lower address byte data out high-impedance 23 32 don?t care so si sck cs 0 23456789101112131415161718192021 22 1 00 a8 0 0 0 0a7654 1a0 76543210 instruction lower address byte data byte high-impedance 23 32 1 t wc si cs 91011 14151617181920212223 24 00 a8 0 0 0 01a7654 210 76543210 instruction lower address byte data byte 1 sck 0 234567 18 si cs 34 35 36 39 40 76543210 data byte n (16 max) sck 25 27 28 29 30 31 32 26 33 76543210 data byte 3 76543210 data byte 2 37 38 3 13
? 2003 microchip technology inc. ds21204d-page 9 25aa040/25lc040/25c040 3.4 write enable (wren) and write disable (wrdi) the 25xx040 contains a write enable latch. see table 3-3 for the write-protect functionality matrix. this latch must be set before any write operation will be completed internally. the wren instruction will set the latch, and the wrdi will reset the latch. the following is a list of conditions under which the write enable latch will be reset: power-up wrdi instruction successfully executed wrsr instruction successfully executed write instruction successfully executed wp line is low figure 3-4: write enable sequence figure 3-5: write disable sequence sck 0 234567 1 si high-impedance so cs 01 0000 0 1 sck 0 234567 1 si high-impedance so cs 01 0000 0 1 0
25aa040/25lc040/25c040 ds21204d-page 10 ? 2003 microchip technology inc. 3.5 read status register (rdsr) the rdsr instruction provides access to the status register. the status register may be read at any time, even during a write cycle. the status register is formatted as follows: the write-in-process (wip) bit indicates whether the 25xx040 is busy with a write operation. when set to a ? 1 ?, a write is in progress, when set to a ? 0 ?, no write is in progress. this bit is read only. the write enable latch (wel) bit indicates the status of the write enable latch. when set to a ? 1 ?, the latch allows writes to the array, when set to a ? 0 ?, the latch prohibits writes to the array. the state of this bit can always be updated via the wren or wrdi commands regardless of the state of write protection on the status register. this bit is read only. the block protection (bp0 and bp1) bits indicate which blocks are currently write-protected. these bits are set by the user issuing the wrsr instruction. these bits are nonvolatile. see figure 3-6 for rdsr timing sequence. 3.6 write status register (wrsr) the wrsr instruction allows the user to select one of four levels of protection for the array by writing to the appropriate bits in the status register. the array is divided up into four segments. the user has the ability to write-protect none, one, two, or all four of the segments of the array. the partitioning is controlled as illustrated in table 3-2. see figure 3-7 for wrsr timing sequence. table 3-2: array protection figure 3-6: read status register sequence figure 3-7: write status register sequence 7654 3 2 1 0 xxxx bp1 bp0 wel wip bp1 bp0 array addresses write-protected 00 none 01 upper 1/4 (0180h - 01ffh) 10 upper 1/2 (0100h - 01ffh) 11 all (0000h - 01ffh) so si cs 91011 12131415 11 0 0 0 0 00 7654 2 10 instruction data from status register high-impedance sck 0 234567 1 8 3 so si cs 91011 12131415 01 0 0 0 0 00 7654 210 instruction data to status register high-impedance sck 0 234567 1 8 3
? 2003 microchip technology inc. ds21204d-page 11 25aa040/25lc040/25c040 3.7 data protection the following protection has been implemented to prevent inadvertent writes to the array: the write enable latch is reset on power-up a write enable instruction must be issued to set the write enable latch after a byte write, page write or status register write, the write enable latch is reset cs must be set high after the proper number of clock cycles to start an internal write cycle access to the array during an internal write cycle is ignored and programming is continued the write enable latch is reset when the wp pin is low 3.8 power-on state the 25xx040 powers on in the following state: the device is in low-power standby mode (cs = 1 ) the write enable latch is reset so is in high-impedance state a low level on cs is required to enter active state table 3-3: write-protect functionality matrix wp wel protected blocks unprotected blocks status register low x protected protected protected high 0 protected protected protected high 1 protected writable writable
25aa040/25lc040/25c040 ds21204d-page 12 ? 2003 microchip technology inc. 4.0 packaging information 4.1 package marking information xxxxxxxx xxxxxnnn yyww 8-lead pdip (300 mil) example: 8-lead tssop example: 8-lead soic (150 mil) example: xxxxxxxx xxxxyyww nnn xxxx xyww nnn 25aa040 i/pnnn yyww 25aa040 i/snyyww nnn 5a4x iyww nnn legend: xx...x customer specific information* y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * standard picmicro device marking consists of microchip part number, year code, week code, and traceability code. for picmicro device marking beyond this, certain price adders apply. please check with your microchip sales office. for qtp devices, any special marking adders are included in qtp price.
? 2003 microchip technology inc. ds21204d-page 13 25aa040/25lc040/25c040 8-lead plastic dual in-line (p) ? 300 mil (pdip) b1 b a1 a l a2 p e eb c e1 n d 1 2 units inches* millimeters dimension limits min nom max min nom max number of pins n 88 pitch p .100 2.54 top to seating plane a .140 .155 .170 3.56 3.94 4.32 molded package thickness a2 .115 .130 .145 2.92 3.30 3.68 base to seating plane a1 .015 0.38 shoulder to shoulder width e .300 .313 .325 7.62 7.94 8.26 molded package width e1 .240 .250 .260 6.10 6.35 6.60 overall length d .360 .373 .385 9.14 9.46 9.78 tip to seating plane l .125 .130 .135 3.18 3.30 3.43 lead thickness c .008 .012 .015 0.20 0.29 0.38 upper lead width b1 .045 .058 .070 1.14 1.46 1.78 lower lead width b .014 .018 .022 0.36 0.46 0.56 overall row spacing eb .310 .370 .430 7.87 9.40 10.92 mold draft angle top 51015 51015 mold draft angle bottom 51015 51015 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed jedec equivalent: ms-001 drawing no. c04-018 .010? (0.254mm) per side. significant characteristic
25aa040/25lc040/25c040 ds21204d-page 14 ? 2003 microchip technology inc. 8-lead plastic small outline (sn) ? narrow, 150 mil (soic) foot angle f 048048 15 12 0 15 12 0 mold draft angle bottom 15 12 0 15 12 0 mold draft angle top 0.51 0.42 0.33 .020 .017 .013 b lead width 0.25 0.23 0.20 .010 .009 .008 c lead thickness 0.76 0.62 0.48 .030 .025 .019 l foot length 0.51 0.38 0.25 .020 .015 .010 h chamfer distance 5.00 4.90 4.80 .197 .193 .189 d overall length 3.99 3.91 3.71 .157 .154 .146 e1 molded package width 6.20 6.02 5.79 .244 .237 .228 e overall width 0.25 0.18 0.10 .010 .007 .004 a1 standoff 1.55 1.42 1.32 .061 .056 .052 a2 molded package thickness 1.75 1.55 1.35 .069 .061 .053 a overall height 1.27 .050 p pitch 8 8 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d n p b e e1 h l c 45 f a2 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-012 drawing no. c04-057 significant characteristic
? 2003 microchip technology inc. ds21204d-page 15 25aa040/25lc040/25c040 8-lead plastic thin shrink small outline (st) ? 4.4 mm (tssop) 10 5 0 10 5 0 mold draft angle bottom 10 5 0 10 5 0 mold draft angle top 0.30 0.25 0.19 .012 .010 .007 b lead width 0.20 0.15 0.09 .008 .006 .004 c lead thickness 0.70 0.60 0.50 .028 .024 .020 l foot length 3.10 3.00 2.90 .122 .118 .114 d molded package length 4.50 4.40 4.30 .177 .173 .169 e1 molded package width 6.50 6.38 6.25 .256 .251 .246 e overall width 0.15 0.10 0.05 .006 .004 .002 a1 standoff 0.95 0.90 0.85 .037 .035 .033 a2 molded package thickness 1.10 .043 a overall height 0.65 .026 p pitch 8 8 n number of pins max nom min max nom min dimension limits millimeters* inches units a2 a a1 l c f 1 2 d n p b e e1 foot angle f 048048 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .005? (0.127mm) per side. jedec equivalent: mo-153 drawing no. c04-086 significant characteristic
25aa040/25lc040/25c040 ds21204d-page 16 ? 2003 microchip technology inc. appendix a: revision history revision d corrections to section 1.0, electrical characteristics.
? 2003 microchip technology inc. ds21204d-page 17 25aa040/25lc040/25c040 on-line support microchip provides on-line support on the microchip world wide web site. the web site is used by microchip as a means to make files and information easily available to customers. to view the site, the user must have access to the internet and a web browser, such as netscape ? or microsoft ? internet explorer. files are also available for ftp download from our ftp site. connecting to the microchip internet web site the microchip web site is available at the following url: www.microchip.com the file transfer site is available by using an ftp ser- vice to connect to: ftp://ftp.microchip.com the web site and file transfer site provide a variety of services. users may download files for the latest development tools, data sheets, application notes, user's guides, articles and sample programs. a vari- ety of microchip specific business information is also available, including listings of microchip sales offices, distributors and factory representatives. other data available for consideration is: latest microchip press releases technical support section with frequently asked questions design tips device errata job postings microchip consultant program member listing links to other useful web sites related to microchip products conferences for products, development systems, technical information and more listing of seminars and events systems information and upgrade hot line the systems information and upgrade line provides system users a listing of the latest versions of all of microchip's development systems software products. plus, this line provides information on how customers can receive the most current upgrade kits. the hot line numbers are: 1-800-755-2345 for u.s. and most of canada, and 1-480-792-7302 for the rest of the world. 042003
25aa040/25lc040/25c040 ds21204d-page 18 ? 2003 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to : technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds21204d 25aa040/25lc040/25c040 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document?
? 2003 microchip technology inc. ds21204d-page 19 25aa040/25lc040/25c040 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . part no. x /xx xxx pattern package temperature range device device: 25aa040: 4096-bit 1.8v spi serial eeprom 25aa040t: 4096-bit 1.8v spi serial eeprom (tape and reel) 25xx040x: 4096-bit 1.8v spi serial eeprom in alternate pinout (st only) 25aa040xt:4096-bit 1.8v spi serial eeprom in alternate pinout tape and reel (st only) 25lc040: 4096-bit 2.5v spi serial eeprom 25lc040t: 4096-bit 2.5v spi serial eeprom (tape and reel) 25lc040x: 4096-bit 2.5v spi serial eeprom in alternate pinout (st only) 25lc040xt:4096-bit 2.5v spi serial eeprom in alternate pinout tape and reel (st only) 25c040: 4096-bit 5.0v spi serial eeprom 25c040t: 4096-bit 5.0v spi serial eeprom (tape and reel) 25c040x: 4096-bit 5.0v spi serial eeprom in alternate pinout (st only) 25c040xt: 4096-bit 5.0v spi serial eeprom in alternate pinout tape and reel (st only) temperature range: i = -40 c to+85 c e = -40 c to +125 c package: p = plastic dip (300 mil body), 8-lead sn = plastic soic (150 mil body), 8-lead st = plastic tssop (4.4 mm body), 8-lead examples: a) 25aa040-i/p: industrial temp., pdip package b) 25aa040-i/sn: industrial temp., soic package c) 25aa040t-i/sn: tape and reel, industrial temp., soic package d) 25aa040x-i/st: alternate pinout, industrial temp., tssop package e) 25aa040xt-i/st: alternate pinout, tape and reel, industrial temp., tssop package f) 25lc040-i/p: industrial temp., pdip package g) 25lc040-i/sn: industrial temp., soic package h) 25lc040t-i/sn: tape and reel, industrial temp., soic package i) 25lc040x-i/st: alternate pinout, industrial temp., tssop package j) 25lc040xt-i/st: alternate pinout, tape and reel, industrial temp., tssop package k) 25c040-i/p: industrial temp., pdip package l) 25c040-i/sn: industrial temp., soic package m) 25c040t-i/sn: tape and reel, industrial temp., soic package n) 25c040x-i/st: alternate pinout, industrial temp., tssop package o) 25c040xt-i/st: alternate pinout, tape and reel, industrial temp., tssop package p) 25c040-e/p: extended temp., pdip package q) 25c040-e/sn: extended temp., soic package r) 25c040t-e/sn: tape and reel, extended temp., soic package s) 25c040x-e/st: alternate pinout, extended temp., tssop package t) 25c040xt-e/st: alternate pinout, tape and reel, extended temp., tssop pack- age
25aa040/25lc040/25c040 ds21204d-page 20 ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. ds21204d-page 21 information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. it is your responsibility to ensure that your application m eets with your specifications. no representation or warranty is given and no liability is assumed by microchip technol ogy incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of microc hip?s products as critical com- ponents in life support systems is not authorized except with express written approval by mi crochip. no licenses are con- veyed, implicitly or otherwis e, under any intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , mplab, pic, picmicro, picstart, pro mate and powersmart are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. amplab, filterlab, micro id , mxdev, mxlab, picmaster, seeval and the embedded control solutions company are registered trademarks of micr ochip technology incorporated in the u.s.a. application maestro, dspicdem, dspicdem.net, ecan, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, microport, migratable memory, mpasm, mplib, mplink, mpsim, pickit, picdem, picdem.net, powercal, powerinfo, powermate, powertool, rflab, rfpic, select mode, smartsensor, smartshunt, smar ttel and total endurance are trademarks of microchip technology incorporated in the u.s.a. and other countries. serialized quick turn programming (sqtp) is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned he rein are property of their respective companies. ? 2003, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specifications contained in microchip's data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconductor manufacturer c an guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are comm itted to continuously improving the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received qs-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona in july 1999 and mountain view, california in march 2002. the company?s quality system processes and procedures are qs-9000 compliant for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms, microperipherals, non-volatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001 certified.
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